View IDT8P34S1208I_8827981.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet 1:8 lvds output 1.8v fanout buffer IDT8P34S1208I idt8p34s1208nbgi revision a january 22, 2014 1 ?2014 integrated device technology, inc. general description the IDT8P34S1208I is a high-performance differential lvds fanout buffer. the device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. the IDT8P34S1208I is characterized to operate from a 1.8v power supply. guaranteed output-to- output and part-to-part skew characteristics make the IDT8P34S1208I ideal for those clock distribution applications demandin g well-defined performance and repeatability. two selectable differential inputs and eight low skew outputs are available. the integrat ed bias voltage reference enables easy interfacing of single-ended signals to the device inputs. the device is optimized for low power consumption and low additive phase noise. features ? eight low skew, low additive jitter lvds output pairs ? two selectable, differential clock input pairs ? differential clk, nclk pairs can accept the following differential input levels: lvds, cml ? maximum input clock frequency: 1.2ghz (maximum) ? lvcmos/lvttl interface levels for the control input select pin ? output skew: 20ps (typical) ? propagation delay: 315ps (typical) ? low additive phase jitter, rms; f ref = 156.25mhz, v pp = 1v, 12khz - 20mhz: 41fs (typical) ? full 1.8v supply voltage ? lead-free (rohs 6), 28-lead vfqfn packaging ? -40c to 85c ambient operating temperature block diagram. pin assignment f ref v ref0 clk0 nclk0 clk1 nclk1 sel v ref1 q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7 nq7 voltage v dd v dd reference voltage reference nq3 q3 nq2 q2 nq1 q1 v dd 21 20 19 18 17 16 15 IDT8P34S1208I 28-lead vfqfn 5.0mm x 5.0mm x 0.75mm package body 3.25mm x 3.25mm epad size nb package top view q4 22 14 gnd nq4 23 13 nq0 q5 24 12 q0 nq5 25 11 v ref0 q6 26 10 nclk0 nq6 27 9 clk0 v dd 28 8 v dd 1234567 gnd q7 nq7 sel clk1 nclk1 v ref1
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 2 ?2014 integrated device technology, inc. pin description and pin characteristic tables table 1. pin descriptions note 1. 1. pulldown and pullup refers to an internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 14 gnd power power supply pin. 2, 3 q7, nq7 output differential output pair 7. lvds interface levels. 4 sel input pulldown reference select control pin. see table 3 for function. lvcmos/lvttl interface levels. 5 clk1 input pulldown non-inverting differential clock/data input 1. 6 nclk1 input pullup/ pulldown inverting differential clock/data input 1. v dd /2 default when left floating. 7v ref1 output bias voltage reference. provides an input bias voltage for the clk1, nclk1 input pair in ac-coupled applications. refer to figures 2b and 2c for applicable ac-coupled input interfaces. 8, 15, 28 v dd power power supply pin. 9 clk0 input pulldown non-inverting differential clock/data input 0. 10 nclk0 input pullup/ pulldown inverting differential clock/data input 0. v dd /2 default when left floating. 11 v ref0 output bias voltage reference. provides an input bias voltage for the clk0, nclk0 input pair in ac-coupled applications. refer to figures 2b and 2c for applicable ac-coupled input interfaces. 12, 13 q0, nq0 output differential output pair 0. lvds interface levels. 16, 17 q1, nq1 output differential output pair 1. lvds interface levels. 18, 19 q2, nq2 output differential output pair 2. lvds interface levels. 20, 21 q3, nq3 output differential output pair 3. lvds interface levels. 22, 23 q4, nq4 output differential output pair 4. lvds interface levels. 24, 25 q5, nq5 output differential output pair 5. lvds interface levels. 26, 27 q6, nq6 output differential output pair 6. lvds interface levels. table 2. pin characteristics symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ? table 3. sel input function table note 1. 1. sel is an asynchronous control. input operation sel 0 clk0, nclk0 is the selected differential clock input. 1 clk1, nclk1 is the selected differential clock input.
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 3 ?2014 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or an y conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating condit ions for extended periods may affect product reliability. note 1: according to jedec js-001-2012/jesd22-c101e. dc electrical characteristics item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma input sink/source, i ref 2ma maximum junction temperature, t j,max 125c storage temperature, t stg -65c to 150c esd - human body model, note 1 2000v esd - charged device model, note 1 1500v table 4a. power supply dc characteristics, v dd = 1.8v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v dd power supply voltage 1.71 1.8 1.89 v i dd power supply current q0 to q7 terminated 100 ? between nqx, qx 120 140 ma table 4b. lvcmos/lvttl dc characteristics, v dd = 1.8v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd * 0.65 v dd + 0.3 v v il input low voltage -0.3 v dd * 0.35 v i ih input high current sel v dd = v in = 1.89v 150 a i il input low current sel v dd = 1.89v, v in = 0v -10 a
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 4 ?2014 integrated device technology, inc. table 4c. differential inputs characteristics, v dd = 1.8v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units i ih input high current clk0, nclk0, clk1, nclk1 v in = v dd = 1.89v 150 a i il input low current clk0, clk1 v in = 0v, v dd = 1.89v -10 a nclk0, nclk1 v in = 0v, v dd = 1.89v -150 a v ref reference voltage for input bias note 1. 1. v ref specification is applicable to the ac -coupled input interfaces shown in figures 2b and 2c. i ref = +100a, v dd = 1.8v 0.9 1.30 v v pp peak-to-peak voltage v dd = 1.89v 0.2 1.0 v v cmr common mode input voltage note 2. note 3. 2. common mode input voltage is defined as crosspoint voltage. 3. v il should not be less than -0.3v and v ih should not be higher than v dd . 0.9 v dd ? (v pp /2) v table 4d. lvds dc characteristics, v dd = 1.8v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v od differential output voltage outputs loaded with 100 ? 247 350 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.0 1.23 1.4 v ? v os v os magnitude change 50 mv note3.
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 5 ?2014 integrated device technology, inc. ac electrical characteristics table 5. ac electrical characteristics, v dd = 1.8v 5%, t a = -40c to 85 note 1. 1. electrical parameters are guaranteed over the specified ambient operating temperatur e range, which is established when the de vice is mounted in a test socket with maintained transverse airflow grea ter than 500 lfpm. the device wi ll meet specifications after th ermal equi- librium has been reached under these conditions. symbol parameter test conditio ns minimum typical maximum units f ref input frequency clk[0:1], nclk[0:1] 1.2 ghz ? v/ ? t input edge rate clk[0:1], nclk[0:1] 1.5 v/ns t pd propagation delay note 2. 2. measured from the differential input crossing point to the differential output crossing point clk[0:1]; nclk[0:1] to any qx, nqx for v pp = 0.4v 190 315 400 ps t sk(o) output skew note 3. note 4. 3. defined as skew between outputs at the sa me supply voltage and with equal load c onditions. measured at th e differential cross points. 4. this parameter is defined in accordance with jedec standard 65. 20 40 ps t sk(i) input skew 10 45 ps t sk(p) pulse skew f ref = 100mhz 6 20 ps t sk(pp) part-to-part skew note 5. 5. defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature a nd with equal load conditions. using the same type of inputs on each de vice, the outputs are measured at the differential cross points. 250 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section f ref = 122.88mhz square wave, v pp = 1v, integration range: 1khz ? 40mhz 122 221 fs f ref = 122.88mhz square wave, v pp = 1v, integration range: 10khz ? 20mhz 88 110 fs f ref = 122.88mhz square wave, v pp = 1v, integration range: 12khz ? 20mhz 84 110 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 1khz ? 40mhz 57 107 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 10khz ? 20mhz 41 78 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 12khz ? 20mhz 41 78 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 1khz ? 40mhz 55 112 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 10khz ? 20mhz 40 85 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 12khz ? 20mhz 40 85 fs t r / t f output rise/ fall time 10% to 90% outputs loaded with 100 ? 305 400 ps 20% to 80% outputs loaded with 100 ? 175 260 ps mux isolation mux isolation note 6. 6. qx, nqx outputs measured differentially. see mux isolation diagram in the parameter measurement information section. f ref = 100mhz 80 db
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 6 ?2014 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundament al frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications , phase noise measurements have issues relating to the limitations of the measurement equipment. the noise floor of the equipment can be higher or lower than the noise floor of the device. additive phase noise is dependent on both the noise floor of the input source and measurement equipment. measured using a rohde & schwarz sma 100 a signal generator as the input source. additive phase jitter @ 122.88mhz 10khz to 20mhz ? 88fs (typical) offset from carrier frequency (hz) ssb phase noise dbc/hz
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 7 ?2014 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundament al frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications , phase noise measurements have issues relating to the limitations of the measurement equipment. the noise floor of the equipment can be higher or lower than the noise floor of the device. additive phase noise is dependent on both the noise floor of the input source and measurement equipment. measured using a wenzel 156.25mhz oscillator as the input source. additive phase jitter @ 156.25mhz 10khz to 20mhz ? 41fs (typical) offset from carrier frequency (hz) ssb phase noise dbc/hz
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 8 ?2014 integrated device technology, inc. parameter measureme nt information 1.8v lvds output load test circuit input skew part-to-part skew differential input level output skew pulse skew v dd t pd2 t pd1 tsk(i) = |t pd1 - t pd2 | tsk(i) nclk1 clk1 nq[0:7] q[0:7] nclk0 clk0 t sk(pp) part 1 part 2 qx nqx qy nqy v dd gnd nclk[0:1] clk[0:1] qx nqx qy nqy t plh t phl tsk(p) = |t phl - t plh | clk[0:1] nclk[0:1] qy nqy
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 9 ?2014 integrated device technology, inc. parameter measurement in formation, continued propagation delay output rise/fall time differential output voltage setup mux isolation output rise/fall time offset voltage setup t pd nq[0:7] q[0:7] nclk[0:1] clk[0:1] nq[0:7] q[0:7] 20% 80% 80% 20% t r t f v od amplitude (db) a0 spectrum of output signal q mux _isolation = a0 ? a1 (fundamental) frequency ? mux selects other input mux selects active input clock signal a1 10% 90% 90% 10% t r t f v od nq[0:7] q[0:7]
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 10 ?2014 integrated device technology, inc. applications information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that th e sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, match ed termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be in creased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the use of a differential input, both the clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. outputs: lvds outputs unused lvds outputs must either have a 100 ? differential termination or have a 100 ? pullup resistor to v dd in order to ensure proper device operation.
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 11 ?2014 integrated device technology, inc. 1.8v differential clock input interface the clk /nclk accepts lvds and other differential signals. the differential input signal must meet both the v pp and v cmr input requirements. figures 2a to 2d show interface examples for the clk /nclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. differential input driven by an lvds driver - dc coupling figure 2c. differential input driven by an lvds driver - ac coupling figure 2b. differential input driven by an lvpecl driver - ac coupling figure 2d. differential input driven by a cml driver
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 12 ?2014 integrated device technology, inc. lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output struct ures: current source and voltage source. the standard termination schematic as shown in figure 3a can be used with either type of output structure. figure 3b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds termination lvds driver lvds driver lv d s receiver lv d s receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 3a. standard termination figure 3b. optional termination
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 13 ?2014 integrated device technology, inc. vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 14 ?2014 integrated device technology, inc. power considerations this section provides information on power dissipation and junction temperature for the IDT8P34S1208I. equations and example ca lculations are also provided. 1. power dissipation. the total power dissipation for the IDT8P34S1208I is the sum of the core power plus the output power dissipation due to the loa d. the following is the power dissipation for v dd = 1.8v + 5% = 1.89v, which gives worst case results. the maximum current at 85c is as follows: i dd_max = 126ma ?power (core)max = v dd_max * i dd_max = 1.89v * 126ma = 238.14mw total power _max = 238.14mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + ta tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the app ropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 46.2c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.238w * 46.2c/w = 96c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 28 lead vfqfn ? ja at 0 air flow meters per second 012 multi-layer pcb, jedec standard te st boards 46.2c/w 39.4c/w 37.1c/w
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 15 ?2014 integrated device technology, inc. reliability information transistor count the transistor count for the IDT8P34S1208I is: 976 table 7. ? ja vs. air flow table for a 28 lead vfqfn ? ja at 0 air flow meters per second 012 multi-layer pcb, jedec standard te st boards 46.2c/w 39.4c/w 37.1c/w
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 16 ?2014 integrated device technology, inc. 28 lead vfqfn package out line and package dimensions
IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer idt8p34s1208nbgi revision a january 22, 2014 17 ?2014 integrated device technology, inc. ordering information table 8. ordering information part/order number marking package shipping packaging temperature 8p34s1208nbgi p34s1208nbgi ?lead-free? 28 lead vfqfn tray -40 ? c to 85 ? c 8p34s1208nbgi8 p34s1208nbgi ?lead-free? 28 lead vfqfn tape & reel -40 ? c to 85 ? c
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2014. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales netcom@idt.com +480-763-2056 we?ve got your timing solution IDT8P34S1208I data sheet 1:8 lvds output 1.8v fanout buffer

▲Up To Search▲

Price & Availability of IDT8P34S1208I

	To Download IDT8P34S1208I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .